DC power supply with compensated current reference

ABSTRACT

A power supply 10 providing a DC output voltage comprises a voltage input circuit 11, a charge buildup and transfer circuit 14, a switch including SCR3 for selectively interconnecting the input circuit 11 and the charge buildup and transfer circuit 14, a trigger circuit including a unijunction transistor gating circuit 16 for triggering the SCR3, and a sensing circuit 22 including a current reference 26 for sensing the current output to the load 38 and comparing the output to current reference 26 while providing a comparison signal to the trigger circuit 16 so as to modify the triggering of SCR3 and thus the interconnection of the voltage input circuit 11 and the current buildup and transfer circuit 14.

FIELD OF THE INVENTION

The present invention relates to power supplies and more particularly, to a power supply for producing a precise constant output irrespective of variations in the AC input voltage provided thereto and irrespective of changes in the load.

BACKGROUND OF THE INVENTION

A number of power supply arrangements are presently commercially available to provide a precise output irrespective of the variations in AC input voltage and changes in the load. As disclosed in U.S. Pat. No. 3,414,798 issued to Jorgen L. Nielsen on Dec. 3, 1968, one type of power supply is a switching device for selectively turning on and off the input voltage. In this power supply the input voltage is provided to rectifying and filtering networks which develop the desired output voltages. A feedback control loop samples the output of the power supply and provides the sampled voltage output to a comparison circuit which compares the sampled output with a reference voltage. A control signal is developed by the comparison circuit which is used to operate the switching device to switch on and off the input voltage at a rate to make the output voltage constant.

The prior art power supplies, however, have disadvantages in that generally it is more difficult to sample voltage output as voltage and make comparison thereof than to sample voltage outputs as current and make comparison thereof. Further such prior art devices provide no compensating signal to the reference source to compensate for the error signal. Also there is generally no consideration given to synchronizing the timing of switching on the input voltage at the same point in the cycle thereof in order to provide a precise voltage output.

SUMMARY OF THE INVENTION

The present invention is directed to overcoming the disadvantages of the prior art.

A preferred embodiment of the power supply of the invention includes a voltage input means for providing input voltage, charge buildup and transfer means for building up and transferring output to a load, trigger means for triggering the interconnection of the voltage input means and the charge buildup and transfer means, and sensing means for sensing the output to a load and comparing the output to a reference and providing a signal based on this comparison to the trigger means so as to modify the triggering of the interconnection of the voltage input means and the charge buildup and transfer means.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is an embodiment of the power supply of the invention.

FIG. 2 is a graph showing the charging cycle of the voltage buildup and transfer means of the invention.

FIG. 3 shows a simplified representation of the sensing circuit of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

With reference to the figures, and in particular to FIG. 1, an embodiment of the Power Supply 10 of the invention is depicted which can be used, for example, to power a microprocessor requiring a steady 5-volt DC input. Power supply 10 includes the following subcomponents: high voltage input circuit 11 comprising AC power input circuitry 12 and charge buildup and transfer circuitry 14, triggering circuit 16 including opto-coupler 18, output filter and load circuitry 20, and sensing circuit 22 including protection circuit 24.

In a preferred embodiment, the individual components are identified and valued as follows:

CAPACITORS

C₁ : 1050 microfarads; 330 WVDC, electrolytic

C₂ : 0.0022 microfarad; 600 WVDC

C₃ : 0.015 microfarad; 50 WVDC

C₄ : 0.057 microfarad; 1600 WVDC

C₅ : 0.33 microfarad; 100 WVDC

C₆ : 0.33 microfarad; 100 WVDC

C₇ : 6200 microfarads; 16 VDC; Mallory VPR622V016L3C

C₈ : 6200 microfarads; 16 VDC; Mallory VPR622V016L3C

C₉ : two C₈ capacitors in parallel

RESISTORS

R₁ : 200 ohm, 5 watt

R₂ : 30 ohm, 1/8 watt

R₃ : 15 K-ohm, 1/8 watt

R₄ : 1 K-ohm, 1/8 watt

R₅ : 470 K-ohm, 1/8 watt

R₆ : 47 ohm, 1/2 watt

R₇ : 12 K-ohm, 5 watt

R₈ : 70 ohm, 1/8 watt

R₉ : 470 ohm, 1/8 watt

R₁₀ : 100 ohm, 1/8 watt

R₁₁ : 40 ohm, 1/8 watt

R₁₂ : 0.5 ohm, 14 watt

R₁₃ : 0.05 ohm, 5 watt

R₁₄ : 1.3 ohm, 2 watt

R₁₅ : 1.3 ohm, 2 watt

R₁₆ : 0.001 ohm, short segment of 18 gauge wire

R₁₇ : 500 ohm, 1/4 watt potentiometer

R₁₈ : 1000 ohm potentiometer, 1/8 watt

R₁₉ : 25 K-ohm potentiometer adjusted to 6.8 K-ohm, 1/8 watt

R₂₀ : 120 ohm, 1/8 watt

R₂₁ : 470 ohm, 1/8 watt

INDUCTORS

L₅ : Toroidal Permalloy (molybdenum) powder core, about 0.4 microhenrys

L₆ : Toroidal Permalloy (molybdenum) powder core, about 0.2 microhenrys

TRANSFORMER Toroidal powder core

Core: Arnold Engineering A123068-2

L₁ : 36 turns, #16 wire; closely wound in 2 layers of 18 turns each

L₂ : 171 turns, #16 wire; uniformly wound around the core in 2 layers

L₃ : 5 turns, #10 wire; closely wound in one layer, located opposite L₁

L₄ : 5 turns, #16 wire; 3 coils connected in parallel, covering approximately one-third the core circumference opposite L₁

ZENER DIODES

Z₁ : 6.2 volt Zener, 1 watt

Z₂ : 5.1 volt Zener, 1 watt

Z₃ : 13 volt Zener, 1 watt

DIODES

D₁ : IN914

D₂ : SK9000 (RCA)

D₃ : IN914

D₄ : IN914

D₅ : VARO:VSK231

D₆ : VARO:VSK231

D₇ : IN914

D₈ : IN914

D₉ : IN914

D₁₀ : IN914

SILICONE CONTROLLED RECTIFIERS (THYRISTORS)

SCR₁ : SK3627

SCR₂ : MCR 3918-6

SCR₃ : SK3042

UNIJUNCTION TRANSISTORS

UJT1: ECG 6409 (Sylvania)

UJT2: ECG 6409 (Sylvania)

Opto-couplers 18: ECG3040

NFET 26: Radio Shack Cat. No. 276-1734, adjustable current source

T₁ : Darlington transistor NPN, Radio Shack Cat. No. 276-2060

HIGH VOLTAGE INPUT CIRCUIT

The high voltage input circuit 11 includes a full wave rectifier bridge 30 which includes four diodes such as diode 32. The rectifier bridge 30 rectifies a 120 V AC line. Rectifier 30 is provided in parallel with a capacitor C₁. Capacitor C₁ becomes a DC source of unregulated voltage V_(C1) (about 150 volts DC). The high voltage input circuit 11 further includes a transformer coil L₁ which is connected in series with capacitor C₁ and which communicates through a thyristor SCR₃ to the main charging capacitor C₄. The other terminal of C₄ is connected to the ground end of capacitor C₁. The charge buildup and transfer circuit 14 include capacitor C₄ and transformer coil L₂ which define a tank circuit 34 that transfers power to transformer coils L₃ and L₄ as will be explained below.

Initially the voltage V_(C4) across capacitor C₄ is zero. At time zero the SCR₃ is triggered by a current pulse from trigger circuit 16 through the gate G. The line connecting transformer coil L₁ to capacitor C₄ is now closed. The current charging capacitor C₄ through transformer coil L₁ builds up sinusoidally in time until V_(C4) peaks (at about 300 V). At this time the current reverses with capacitor C₄ now trying to charge capacitor C₁. This reverse current flows for a short time until thyristor SCR₃ stops conducting. Capacitor C₄ is now isolated from capacitor C₁ and transformer coil L₁.

Capacitor C₄ starts discharging through transformer coil L₂. In fact, capacitor C₄ starts discharging through transformer coil L₂ even during the charging of capacitor C₄, but because transformer coil L₂ is much larger than transformer coil L₁, the current through coil L₂ is smaller, therefore allowing the voltage V_(C4) of capacitor C₄ to remain higher than V_(C1) across capacitor C₁ for a long enough period to allow thyristor SCR₃ to turn off. During the charging and the discharging of capacitor C₄, whenever the biasing permits, diode D₅ will conduct current to the filtering and load circuits 20.

Eventually, due to the tank circuit 34 formed by capacitor C₄ and coil L₂, the voltage V_(C4) across capacitor C₄ will go negative up to a voltage that permits diode D₆ to conduct current to the filtering and load circuits 20. The thyristor SCR₃ remains turned off.

The tank circuit 34 can continue to oscillate, transferring decreasing amounts of energy alternatively through diodes D₅ and D₆. The currents through diodes D₅ and D₆ and the voltage across coils L₃ and L₄ are averaged out by the inductors L₅ and L₆ and capacitors C₇, C₈ and C₉ which comprise the output filter 36 of filter and load circuitry 20.

It is to be understood that protection is provided by snubbers comprised of resistor R₁ and capacitor C₂, and also resistor R₁₄ and capacitor C₅, and also resistor R₁₅ and capacitor C₆.

THE TRIGGERING CIRCUIT

The triggering circuit 16 is provided in order to trigger the charging of capacitor C₄ by coil L₁ to maintain a constant voltage across the load. The trigger circuit 16 receives an input from the sensing circuit 22 which is proportional to the difference between the desired reference voltage V_(ref) and the voltage provided to the load as measured by a current comparison. This input is in the form of a current which is directly proportional to the size of the voltage difference which is provided to the light emitting diode 40 of opto-coupler 18. This current controls the timing of the triggering of thyristor SCR₃.

The basic elements of the triggering circuit include opto-coupler 18, unijunction transistor UJT₂, capacitor C₃, Zener diode Z₃, diode D₂, thyristor SCR₃ and resistors R₇, R₈ and R₉. Opto-coupler 18, resistor R₇ and diode D₂ provide communication between capacitor C₁ and base 2 of transistor UJT₂. Base 1 of transistor UJT₂ is communicated to the gate G of thyristor SCR₃ through resistor R₈ and with ground through resistors R₈ and R₉ and capacitor C₄. The series combination of resistor R₅ and capacitor C₃ is provided in a parallel arrangement with Zener diode Z₃. This parallel arrangement is communicated between capacitor C₁ with other elements such as thyristor SCR₁ and resistors R₃, R₄ which will be discussed below, and ground.

The interconnection between resistor R₅ and capacitor C₃ communicates with the emitter E₂ of transistor UJT₂. Transistor UJT₂ is constructed such that when the voltage applied to emitter E₂ rises to a certain ratio (intrinsic ratio) of the voltage applied to base 2, the resistance between emitter and base 1 of transistor UJT₂ become very small, allowing capacitor C₃ to discharge across transistor UJT₂. The greater the current from the sensing circuit 22 passing through opto-coupler 18, the higher the voltage at base 2 of transistor UJT₂, and the larger capacitor C₃ must charge before the intrinsic ratio is reached.

Assume the voltage across capacitor C₄ (V_(C4)) is higher than the voltage across the series combination of coil L₁ and C₁ (V_(L1)), the voltage across the triggering circuit 16 is essentially zero because diode D₂ is reverse biased, and capacitor C₃ is completely discharged. In FIG. 1, capacitor C₄ communicates with diode D₂ through zener diodes Z₁, Z₂, Z₃ and resistor R₇. Thus as V_(C4) decreases with respect to V_(L1), eventually diode D₂ is forward biased, and current starts charging up capacitor C₃ and immediately sets the voltage across Zener diode Z₃ to a maximum voltage V_(Z3). Given sufficient time, the voltage across C₃ (V_(C3)) will rise to V_(Z3). When capacitor C₃ has a voltage high enough, emitter E₂ of transistor UJT₂ will conduct and discharge capacitor C₃ through the gate G of thyristor SCR₃ triggering the charging of capacitor C₄. As thyristor SCR₃ conducts, the voltage across the triggering circuit 16 and the voltage across Zener diode Z₃ (V_(Z3)) again drops essentially to substantially zero. This fact resets the transistor UJT₂ very fast for the next triggering and allows resistor R₅ to be small for a fast charging of capacitor C₃. Resistor R₅ can be much smaller than would be possible if V_(Z3) is set constant.

The object of regulation is to maintain a constant voltage V_(L) across the load 38. When the load demands more energy (for instance the load resistance is lowered), the triggering of thyristor SCR₃ must occur more frequently (running at a higher frequency), and/or the voltage V_(C4) must be charged to a higher value.

In this power supply 10, a single control modulates both frequency and charged voltage V_(C4). Since both frequency and voltage are controlled, the frequency need not change very much from full load to almost zero load. In fact the frequency need only change from about 30 KHz to 15 KHz.

FIG. 2 shows the thyristor SCR₃ initially being triggered at time t=0 and how the voltage V_(C4) (measured with reference V=0 volts at the ground end of capacitor C₁) varies with time. The energy transferred to the load during the charging of capacitor C₄ has been neglected.

The next triggering of thyristor SCR₃ can occur any time from t=T₀ (when V_(C4) reaches a minimum) to t=T₁ (when V_(C4) reaches a second maximum V_(C4med) in the free oscillation zone or when V_(C4) =V_(C1), whichever comes first). The maximum charged voltage of capacitor C₄, V_(C4max), depends on where the triggering occurs. If V_(C4t) is the algebraic value of V_(C4) at triggering time, then:

    V.sub.C4max ≃2V.sub.C1 -V.sub.C4t

The energy transferred per cycle is thus:

    1/2C.sub.4 (V.sup.2.sub.C4max -V.sup.2.sub.C4t)=2C.sub.4 V.sub.Cl (V.sub.C1 -V.sub.C4t)

Maximum power occurs at V_(C4t) =-V_(C4min) and zero power occurs and V_(C4t) =+V_(C1).

The time T_(S) where the charging of capacitor C₃ of the triggering circuit 16 begins is always synchronized with the V_(C4) waveform because V_(C3) remains zero from the last triggering up to T_(S) (where V_(C4) begins to be lower than V_(C1)). The charging of C₃ also follows a fixed pattern in time because resistor R₅ and capacitor C₃ and the voltage V_(Z3) at Zener diode Z₃ are constants during this charging. The timing for the next triggering is done by varying the base 2 voltage of transistor UJT₂ which depends on how much current is fed to it from transistor 42 of opto-coupler 18.

The amount of current flowing through the diode 40 of the opto-coupler 18 comes from the sensing circuit 22 (discussed below). The larger the current, the longer it takes capacitor C₃ to build up a charge which is equal to the intrinsic ratio times the voltage at base 2 of transistor UJT₂ and the larger the interval before thyristor SCR₃ is triggered, and thus (FIG. 2) the lower the power output to output filter and load circuit 20. Thus in this embodiment the rate of charging of capacitor C₃ is a constant and the voltage at base 2 of transistor UJT₂ is varied with time, depending on the signal from the sensing circuit 22. A diode D₁ is used to assure that V_(base2) of transistor UJT₂ never goes below V_(Z3) where improper triggering of thyristor SCR₃ may occur (i.e., insufficient voltage to turn on thyristor SCR₃).

Expanding on the above triggering circuit 16 in FIG. 1, series resistors R₃ and R₄ are provided in parallel with thyristor SCR₁, with the gate of thyristor SCR₁ communicating with the interconnection between resistors R₃ and R₄. This parallel arrangement between resistors R₃, R₄ and thyristor SCR₁ communicates capacitor C₁ with resistor R₅ and capacitor C₃ via diode D₂, resistor R₇ and Zener diodes Z₁, Z₂.

At start up, when the input capacitor C₁ is charging up, the rate of increase of V_(C1) is slow, of the order of the AC line frequency times the line voltage. The first discharge of capacitor C₃ through the emitter of transistor UJT₂ will occur at low voltage if R₅ is too small (as is desirable for other than start-up). This will not trigger thyristor SCR₃, therefore the transistor UJT₂ may not reset.

At start-up there must be a large resistor R₃ in series with resistor R₅ to slow down the charging of capacitor C₃, allowing time for the voltage at the base B₂ of the transistor UJT₂ to grow large enough for the triggering of thyristor SCR₃. But resistor R₃ must drop out during normal operation. This is achieved with thyristor SCR₁.

After the first discharge, the thyristor SCR₁ will be turned on at the next charging of capacitor C₃ because the current through resistor R₃ is then large enough to turn on thyristor SCR₁, thus bypassing resistor R₃. Since the turn-off time of thyristor SCR₁ is chosen to be large, SCR₁ is essentially on all the time after the first shooting of capacitor C₃.

A unijunction transistor UJT₁ is also provided with base 2 thereof communicating with the series interconnection between Zener diode Z₁ and Z₂ and base 1 connecting with resistor R₂. The emitter E₁ of transistor UJT₁ communicates with the series interconnection between resistors R₅ and capacitor C₃ and thus with the emitter E₂ of transistor UJT₂.

In practice, thyristor SCR₃ may not turn off when it is triggered at V_(C4) too close to V_(C1) (FIG. 2). Therefore capacitor C₃ has to be discharged by some means when the voltage V_(base2) of transistor UJT₂ imposes a triggering time where V_(C4t) is too close to V_(C1) (around V_(c4med) in FIG. 2).

The value of resistor R₇ is chosen such that thyristor SCR₃ cannot be turn-on when V_(C4t) is near V_(C1). At a low value for V_(C1) -V_(C4), the current through resistor R₇ is primarily channeled into the transistor UJT₂ because V_(Z1) +V_(Z2) +V_(Z3) is higher than the base 2 voltage of UJT₂ (the impedances of the Zener diodes Z₁, Z₂ and Z₃ are at this point very large). Resistor R₇ allows only enough current to maintain V_(base2) of transistor UJT₂ high, preventing the discharge of capacitor C₃ to thyristor SCR₃. The V_(base2) of transistor UJT₁, on the other hand, is deprived of current and fully conducts as the emitter voltage is greater than the intrinsic ratio times the voltage at base 2, discharging capacitor C₃ into resistor R₂.

It is to be understood that over current protection for thyristor SCR₃ is provided by thyristor SCR₂ and resistors R₁₀, R₁₁, R₁₂, R₁₃ and diodes D₃, D₄. As shown in FIG. 1, resistors R₁₂, R₁₃ are provided in tank circuit 34 with thyristor SCR₂ and resistor R₁₀, R₄ and diodes D₃, D₄ connected between tank circuit 34 and capacitor C₁.

It is also to be understood that unwanted voltage fluctuations that can degrade the operation of opto-coupler 18 can be bypassed by connecting the base of its transistor 42 to the interconnection between capacitor C₃ and Zener diode Z₃ (i.e. ground end of C₃) by a series combination of a resistor (larger than 0.5 megaohm) and a capacitor (less than 150 picofarad). Some opto-couplers are less sensitive to these voltage fluctuations than others and may not need the bypassing connection described above.

THE SENSING CIRCUIT

The sensing circuit 22 provides a current to opto-coupler 18 that is proportional to the difference between the desired or reference voltage V_(ref) across the load and the actual voltage across the load V_(L) as measured by a current comparison discussed below. The sensing circuit 22 is principally comprised of resistors R₁₆, R₁₇, R₁₈ and R₁₉, transistor or FET 26 and a current amplification device T₁ comprised of transistor pair 28. Resistor R₁₆ is provided in communication with the load 38 so as to sense the current through load 38 returning to the power supply 10. Potentiometer or Resistor R₁₈ is provided in parallel with resistor 16 and thus sees the same voltage as does resistor R₁₆. The gate of transistor FET 26 is connected to resistor R₁₈ with the source connected to potentiometer or resistor R₁₇ which is connected to one end of resistor R₁₈. The source of transistor FET 26 is connected to potentiometer or resistor R₁₉ and the base of the first transistor 44 in current amplification device T₁. The other terminal of resistor R₁₉ communicates with the positive terminal to which the load 38 is connected. Device T₁ is comprised of two transistors 44, 46, the collectors of which communicate with the diode 40 of opto-coupler 18, and the emitter of the first transistor 44 communicates with the base of the second transistor 46. The emitter of the second transistor 46 communicates with the negative terminal (ground) to which the load 38 is connected.

A simplified representation of the sensing circuit 22 is depicted in FIG. 3. If the V_(BE) of current amplification device T₁ can be considered constant, then:

    i.sub.in =(V.sub.L -V.sub.BE)/R.sub.19,

a linear function of V_(L)

Since i_(out) is constant, the difference Δi can be set to be proportional to (V_(L) =V_(constant)) where V_(constant) is some reference point adjustable by the value of i_(out) :

    Δi=i.sub.in -i.sub.out

thus: ##EQU1## where:

    V.sub.BE +i.sub.out R.sub.19 =V.sub.reference.

After amplification of Δi, the current through the diode 40 of the opto-coupler 18 is roughly proportional to the deviation of V_(L) from V_(reference). The signal from diode 40 creates a current through the transistor 42 of the opto-coupler 18 that is roughly proportional to Δi. This current is fed to the interbase resistance (through base 2) of transistor UJT₂, creating an almost proportional V_(base2) of transistor UJT₂. This V_(base2), in turn, determines when the next triggering of thyristor SCR₃ and will occur as explained above.

One way to improve the regulation is to vary the reference current (i_(out)) by an amount that is proportional to the load to offset the necessary Δi that is needed for regulation. It is convenient to use Δi itself as information on the load to change i_(out), but this is unstable feedback. Therefore, an independent source of information on the load must be used to change i_(out) as the load changes.

This is where the resistance R₁₆ comes into play. R₁₆ essentially senses the current returning from the load 38 to the power supply. The voltage drop across R₁₆ is proportional to the load power demand (since V_(L) is constant). Now, the use of current reference (instead of the traditional voltage reference) by means of a field effect transistor provide a method of adding more current to the reference i_(out) proportionally to the load as shown in FIG. 1. In FIG. 1, resistor R₁₈ is a potentiometer that biases the right amount of voltage from R₁₆ to the gate of transistor FET 26 to exactly offset the Δi used for regulation. The Δi is still there, but it is on top of a higher reference i_(out) such that the resulting V_(L) remains unchanged and thus is not load dependent as this load changes.

The remaining portion of sensing circuit 22 includes diodes D₇, D₈, D₉ and D₁₀ along with resistors R₂₀ and R₂₁. These components protect the power supply, should the user improperly connect lines 50 and 52.

Because physical location of the load 38 and connections thereto varies with use, the sensing lines 50, 52 connecting diode D₉ and resistor R₁₉ to the load 38 cannot be permanently connected. Therefore user mistakes may occur, such as: (a) the user may forget to connect them to the load, or (b) the connections may be loose, or (c) the connecting lines may be broken, or (d) the connections may be to the wrong polarities. In these cases the power supply and the load must be protected from overvoltage because the power supply may run at maximum power if the sensing circuit is not connected properly.

Protection is thus provided for by R₂₀, R₂₁, D₇, D₈, D₉ and D₁₀ as follows.

If the positive line 52 is not connected to resistor R₁₉, then sensing circuit 22 will sense the output voltage at capacitor C₉ instead, through resistor R₂₀, which is connected to capacitor C₉ by line 54. The regulation is then for V_(C9).

If the negative line 50 is not connected to diode D₉, then the current through the opto-coupler 18 will return to the ground of capacitor C₉ through diodes D₇ and D₈ and line 56. Regulation is now for V_(L) with the ground shifted by approximately one forward voltage of a diode. That is, V_(L) is not held constant at V_(reference) but at approximately V_(reference) +V_(Fdiode).

If the polarities of the lines 50, 52 are reversed, then diode D₉ will block or isolate the positive line 52, and diode D₁₀ will return the current through the diode 40 of the opto-coupler 18 to the negative line 50. Since this current is now fairly large, the output power will be very small, depressing V_(L) to a low voltage.

Diode D₉ serves an additional purpose. That is, for increasing the drain voltage of transistor FET 26 so that it can operate properly. To maintain diode D₉ at a constant voltage drop, resistor R₂₁ is used to feed a large current through it.

Further in this sensing circuit 22, potentiometer R₁₇ is used for the adjusting of V_(L) (and thus also i_(out)) in the range of from 4 volts to 8 volts.

It is to be understood that power source 10 can be made programmable to provide a programmable voltage output by replacing the constant current sink by a programmable current sink. The power supply can additionally be made to have a constant current output by replacing resistor R₁₉ by a constant current source such as a field effect transistor.

It also can be appreciated that low voltage rated SCRs can be used for higher input voltage if the voltage is divided and several charge buildup and transfer circuits, such as circuit 14, are provided in parallel across each portion of the divided input.

INDUSTRIAL APPLICABILITY

The operation of the power supply 10 of the invention is as follows. A fully rectified voltage signal is provided to transformer coil L₁. The voltage thereacross is transferred to capacitor C₄ of tank circuit 34 when thyristor SCR₃ is turned on by the trigger circuit 16. When this occurs, the charge is built up across capacitor C₄, and that power is transferred through transformer coil L₂ to transformer coils L₃ and L₄ and therefrom to load 38. Sensing circuit 22 senses the output to the load 38 and provides a signal through opto-coupler 18 to the trigger circuit 16 in order to control the timing of the opening of thyristor SCR₃.

Other aspects and objects of the invention can be obtained from a review of the claims and the figures appended hereto. 

I claim:
 1. A power supply for providing a DC output voltage to a load comprising:voltage input means for providing input voltage; charge buildup and transfer means for building up and transferring an output to a load; switch means for selectively interconnecting the voltage input means and the charge buildup and transfer means; trigger means for triggering the switch means to interconnect the voltage input means and the charge buildup and transfer means; sensing means for sensing current in response to the DC output voltage across the load; a compensated current reference means for providing a current reference; said sensing means having means for comparing the current sensed by the sensing means to the current reference; and signal means for providing a signal based on the comparison between the current sensed and the current reference to the trigger means so as to modify the triggering of the switch means and the interconnection of voltage input means and the charge buildup and transfer means.
 2. The power supply of claim 1 wherein:said sensing means includes a first resistor provided in communication with the load and a current amplification device communicating with the first resistor, and with ground and with the signal means; and wherein said compensated current reference means includes a current sink connected to the connection between said first resistor and said current amplification device.
 3. The power supply of claim 2 including:a second resistor connected between the load and the power supply to sense the current returning to the power supply from the load; a third resistor provided in parallel with the second resistor; the current sink including a transistor communicating with the first resistor, with the transistor having a gate that is biased by the voltage at said third resistor.
 4. A power supply for providing a DC output voltage to a load comprising:voltage input means for providing input voltage; charge buildup and transfer means for building up and transferring a charge; rectifier and filter means for receiving the charge from the charge build-up and transfer means and for providing an output to a load; switch means for selectively interconnecting the voltage input means and the charge buildup and transfer means; reference means for providing a reference; sensing means for sensing the output and for comparing the output to the reference; signal means for providing a signal based on the comparison between the output and the reference; trigger means for turning on the switch means to interconnect the voltage input means and the charge buildup and transfer means; wherein said trigger means includes a threshold means for providing a threshold signal, and means for building up a time-dependent signal to a level relative to the threshold signal such that said trigger means turns on said switch means, wherein at least one of said threshold means and said means for building up a time-dependent signal is provided with the signal from the signal means; and means for synchronizing the starting of the means for building up a time-dependent signal so that the starting occurs at a preselected point on the cycle of voltage oscillation in the charge buildup and transfer means.
 5. A power supply of claim 4 wherein:said synchronizing means starts the means for building up a time-dependent signal at the preselected point when the voltage across the charge buildup and transfer means is substantially equivalent to the voltage of the voltage input means.
 6. The power supply of claim 4 wherein:said means for synchronizing the starting of the means for building up a time-dependent signal includes a diode provided in parallel therewith which interconnects the voltage input means and the charge buildup and transfer means such that when said diode conducts, said time-dependent signal starts building up.
 7. The power supply of claim 4 wherein:said voltage input means includes a first transformer coil and first means for applying a voltage to said first transformer coil; said charge buildup and transfer means includes a second transformer coil and second means for applying a voltage across said second transformer coil; and said switch means includes means for selectively interconnecting said first transformer coil to said second means for applying a voltage across said second transformer coil.
 8. The power of claim 7 wherein:said switch means includes an SCR.
 9. The power supply of claim 7 wherein:said first transformer coil and said second transformer coil are provided on the same transformer core.
 10. The power supply of claim 4 wherein:said voltage input means includes a first transformer coil and first means for applying a voltage to said first transformer coil; said charge buildup and transfer means includes a second transformer coil and second means for applying a voltage across said second transformer coil; said switch means includes an SCR that selectively interconnects said first transformer coil to said second means for applying a voltage across said second transformer coil, said SCR being turned off when the voltage buildup on the second means for applying a voltage across said second transformer is larger than the voltage across the first means for applying voltage.
 11. The power supply of claim 4 including:means for slowing the charging of the means for building up a time-dependent signal at startup so that the voltage of the threshold means can build up to the threshold voltage level to turn on the switch means.
 12. The power supply of claim 11 wherein:said means for slowing the charging of the means for building up a time-dependent signal includes an SCR provided in parallel with a first resistor, both interconnecting said voltage input means to said means for building up a time-dependent signal, said SCR including a gate connected to a terminal of said first resistor which terminal is also connected to said means for building up a time-dependent signal; said first resistor slowing the charging of the means for building up a time-dependent signal at start-up of the power supply until the voltage at the gate builds up to a point that the SCR is turned on, bypassing the first resistor.
 13. The power supply of claim 4 wherein:said sensing means includes a first resistor provided in communication with the load; said reference means includes a current sink connected to said first resistor; and said sensing means further includes a current amplification device communicating with the connection between the current sink and the first resistor, and with ground and with the signal means.
 14. The power supply of claim 13 wherein said current amplification device includes at least one transistor with the base thereof communicating with the interconnection between the first resistor and the constant current sink, the emitter connected to a ground and the collector connected to said signal means.
 15. The power supply of claim 13 including:a second resistor connected between the load and the power supply to sense the current returning to the power supply from the load; a third resistor provided in parallel with the second resistor; and the current sink including a transistor communicating with the first resistor, with the transistor having a gate that is biased by the voltage at said third resistor.
 16. The power supply of claim 4 including:means for discharging the means for building up a time dependent signal when the voltage across said charge buildup and transfer means is close to the voltage at the voltage input means so that the switch means remains turned off.
 17. The power supply of claim 16 wherein said means for discharging the means for building up a time dependent signal includes:a first resistor and a second resistor; a first unijunction transistor with an emitter thereof connected to the threshold means and one terminal of the means for building up a time dependent signal; said first resistor connected between the voltage input means and a base of the first unijunction transistor and said second resistor connected between another base of the first unijunction transistor and another terminal of the means for building up a time dependent signal.
 18. A power supply for providing a DC output voltage to a load comprising:voltage input means for providing input voltage; charge buildup and transfer means for building up and transferring an output to a load; switch means for selectively interconnecting the voltage input means and the charge buildup and transfer means; trigger means for triggering the switch means to interconnect the voltage input means and the charge buildup and transfer means; reference means for providing a reference; sensing means for sensing the output and having means for comparing the output to the reference; signal means for providing a signal based on the comparison between the output and the reference to the trigger means so as to modify the triggering of the switch means and the interconnection of voltage input means and the charge buildup and transfer means; wherein said trigger means includes a unijunction transistor gating circuit having a voltage buildup circuit means for building up a voltage responsive to a voltage across said switch means such that when said trigger means triggers said switch means to conduct, the voltage of the voltage buildup circuit collapses. 